VariaSim enables researchers to analyze the impact of CMOS process variability on the behavior of circuits and systems. To successfully design circuits and systems that tolerate variability, we must understand and quantify the impact of variability on the behavior of real circuits. The traditional approach has been "corner analysis", in which the worst-case delay (e.g., mean delay plus three times the standard deviation) is assumed for every gate along every circuit path. Corner analysis is extremely pessimistic and provides an upper bound on delay that is thus extremely loose. Because no current SSTA tool was publicly available, we have developed and distributed our own tool.
VariaSim is a statistical timing analysis tool that is an extension of previously developed models. VariaSim's inputs are the circuit's netlist and the expected process variability (e.g., the standard deviation of transistor gate length). Given these inputs, VariaSim computes the mean and standard deviation (σ) of the delay through each circuit path. This standard deviation reflects the overall path delay variability that is a result of the low-level process variability. We analytically combine the results from the most critical paths to determine the results for a complete circuit.
We encourage you to read the complete documentation, but here is a brief overview ...
VariaSim's first step is to take a Verilog description of the circuit and use Synopsys Design Compiler (DC) to process it. DC creates a gate-level structural netlist as well as an ordered list of the most critical paths in the circuit. DC determines this list by looking at how many gates are on each path, but it does not provide the inputs necessary to make them switch.
The outputs from DC are used in two different ways:
VariaSim passes the structural gate-level netlist to Cadence Silicon Ensemble, which labels the gates with their relative physical positions in the circuit. VariaSim processes this output from Silicon Ensemble in order to create a grid onto which it can place each gate. This grid is used when considering the spatial correlation of process variability.
There are several steps in this process. First, VariaSim truncates the list of most critical paths, because only a certain percentage of paths can possibly affect the timing of the circuit, even in the presence of significant process variability. Second, for each path in this truncated list, VariaSim tests the circuit to find a set of inputs to make the path switch. If the path cannot be made to switch despite VariaSim's best efforts (this is an NP-hard problem), the path is discarded from the analysis. If the path can be made to switch, VariaSim produces multiple transistor-level netlists of the entire circuit. Third, VariaSim simulates each of these circuit netlists with SPICE, and VariaSim parses the results to determine the sensitivity of circuit performance to the low-level parameters.
Once VariaSim has generated the grid of gates and the results of the sensitivity analysis, it uses Matlab to compute the mean and standard deviation of the delay of each path. VariaSim then uses a previously validated approximation to determine the mean and standard deviation of the delay of the entire circuit.
VariaSim uses commercial CAD tools for various purposes, rather than reinventing them. It thus requires the user to have access to these tools (or comparable tools), which are commonly used in both industry and academia. The commercial tools include Synopsys Design Compiler (for converting Verilog code to gate-level structural netlists), Cadence Silicon Ensemble (for determining the relative physical positions of gates in the structural netlists), SPICE (for circuit simulations), and Matlab (for data analysis).
VariaSim can be downloaded here. VariaSim is released under the GNU General Public Licence (GPL). If your use of this software contributes to a published paper, we request that you (1) cite our summary paper that appears below and (2) e-mail a citation for your published paper to
"VariaSim: Simulating Circuits and Systems in the Presence of Process Variability." Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, and Daniel J. Sorin. Computer Architecture News, volume 35, number 5, December 2007.
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